This application relates to technology for fabricating semiconductor devices having sub-minimum pitch.
In semiconductor processing, the term “pitch” typically refers to a center-to-center spacing between identical features in a semiconductor device, and a minimum pitch is the smallest allowable center-to-center spacing between identical features. Some semiconductor devices require several processes, each having a minimum pitch. For example, a semiconductor device may require a first process having a first minimum pitch P1, and a second process having a second minimum pitch P2. In such instances, the entire device usually has to be manufactured at the largest minimum pitch required by the various constituent processes. In the example described above, if P2>P1, the entire device usually has to be manufactured at the second minimum pitch P2. In these cases, the scaling (and thus cost reduction) of the device is limited by this worst-case process.
An example is a monolithic three-dimensional semiconductor device that includes a magnetoresistive random access memory (MRAM) cell array built above an underlying array of vertically-oriented selectors, such as vertically-oriented transistors or two-terminal selector devices. The underlying selector array can be scaled to pitches limited only by industry-standard patterning techniques (e.g., immersion 193 nm lithography, double patterning, reactive ion etching, etc.), which can currently achieve pitches down to about 30 nm. However, typical MRAM materials cannot be patterned with such minimum pitch techniques, and currently use techniques that limit their pitch to about 65 nm. As a result, the entire monolithic three-dimensional semiconductor device has to be manufactured at the larger pitch required by the MRAM process.